VLSI Engineer • FPGA Developer • Embedded Systems Engineer
Focused on RTL Design, FPGA Development, and Embedded Systems Engineering. I enjoy building reliable digital hardware from architecture design and verification to real-world implementation.
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About
I am an Electronics and Communication Engineering student with a strong passion for VLSI design, embedded systems, FPGA development, and real-time hardware engineering.
My areas of interest include RTL Design, Verilog HDL, digital system architecture, AI-enabled embedded applications, and hardware-software integration for intelligent systems.
I enjoy transforming engineering concepts into practical, efficient, and scalable hardware solutions through innovation, experimentation, and system-level thinking.
Skills
Research
Applying AI, remote sensing, and computer vision techniques to solve practical engineering challenges.
JOURNEY
Representing PALAS initiatives, engaging with students, promoting innovation, and supporting community-driven activities.
Reached the finalist stage by developing and presenting an innovative engineering solution in a competitive hackathon environment.
Coordinating technical events, student engagement activities, and leadership initiatives across the campus community.
Gaining practical experience in secure systems, cybersecurity concepts, and industry workflows.
Projects
Selected FPGA, embedded systems, digital design, and research projects focused on real-world engineering challenges.
Developing a complete UVM verification environment for an open-source DDR4 Memory Controller using SystemVerilog, UVM, constrained-random verification, functional coverage, assertions, scoreboarding, and automated regression testing.
8-bit single-cycle processor designed using Verilog HDL with FPGA implementation and verification.
Research project combining spectral thresholding and CNN segmentation for satellite image cloud detection.
FSM-based UART transmitter designed and verified using Verilog HDL and Vivado simulation.
Automated sensor-driven cleaning system with optimized water usage and intelligent control logic.
Hierarchical cache architecture project focused on memory performance optimization.
Contact
Open to VLSI, Embedded Systems and Hardware Engineering opportunities.
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Developed an 8-bit Single-Cycle Mini RISC Processor using Verilog HDL with ALU, Register File, Control Unit, Program Counter, and Instruction Memory architecture.
Performed RTL Design, Behavioral Simulation, Verification, and FPGA-based debugging using Vivado Design Suite on Basys 3 Artix-7 FPGA.
Implemented instruction execution for ADD, SUB, AND, and OR operations with real-time LED visualization, GitHub Actions CI workflow, and structured hardware project organization.
Focused on designing reliable digital hardware using RTL methodologies and verifying functionality through simulation, waveform analysis, and structured testing. This domain forms the foundation of my VLSI and FPGA development workflow.
Experienced in implementing digital systems on FPGA platforms, covering RTL synthesis, hardware debugging, and real-time validation. FPGA development serves as a practical bridge between digital design concepts and physical hardware realization.
Building intelligent hardware solutions through microcontrollers, sensors, and communication interfaces. My embedded projects focus on real-time control, hardware-software integration, and practical engineering applications.
Utilizing programming languages to develop embedded firmware, automate engineering workflows, and support hardware design and testing activities. Software serves as an essential tool for building efficient and scalable engineering solutions.
Specializing in the design and development of application-specific integrated circuits (ASICs). My expertise includes digital logic design, finite state machine (FSM) design, and register-transfer level (RTL) design using Verilog HDL.
Focused on processor architecture, memory hierarchy, instruction execution, and digital system organization. This domain bridges hardware design with efficient computation and system-level performance.
